1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming self-aligned contacts (SAC) for semiconductor devices such as transistors.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, memory devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Metal-Oxide-Field-Effect-Transistors (MOSFETs) represent one dominant type of circuit element that substantially determines performance of the integrated circuits. MOSFETs are typically either an N-type (NFET) device or a P-type (PFET) device and they are complementary to each other (thus, when both types are used in an integrated circuit product, the technology is referred to as C-MOSFET or CMOS technology). During the fabrication of complex integrated circuits, millions of CMOS transistors, e.g., NFETs and/or PFETs, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET or a PFET is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, referred to as a channel region, disposed between the highly doped source/drain regions in the substrate. The channel length of a MOS transistor is generally considered to be the lateral distance between the source/drain regions.
In modern semiconductor devices, the gate structures are very small and have a very small distance or pitch between adjacent gate structures. As CMOS device dimensions continue to be reduced in size, e.g., 20-30 nm gate lengths and gate pitches on the order of 60-90 nm at the 20 nm CMOS technology node, the formation of conductive contacts to the source/drain regions of a transistor has become very challenging. Such contacts are typically formed by direct patterning techniques using traditional photolithography and etching techniques. Given the decrease in device dimension, device designers have resorted to making the conductive contacts very small so as to have some tolerance or “process margin” for positioning the contact between adjacent gate structures. If the process margin is not large enough with contact holes that are aligned poorly and near the spacer shoulder of gate structures, the spacers on the sidewall of gate structures can be damaged by the plasma oxide etching during contact formation and result in circuit failures due to the “short” between the contact and the gate electrode. However, when using such techniques, the accuracy in forming such contact openings is very critical. Errors in pattern alignment can ultimately result in the formation of conductive contacts that are even smaller than intended by the device designer. As a result, such excessively small conductive contacts, and the resulting underlying metal silicide regions, can increase the resistance of the contact structure and thereby reduce the performance of the resulting transistors and integrated circuit products incorporating such devices. In a worst case scenario, such misalignment can lead to short circuits and total device failure as described.
Another technique that device designers have developed in an effort to meet the challenge of making contact to the source/drain regions of such very small devices involves the formation of so-called self-aligned contacts (SAC). In general, in a self-aligned contact, the configuration of the opening for the contact is essentially defined by the configuration of adjacent structures, e.g., sidewall spacers on adjacent gate structures. The contact opening and the resulting conductive contact are “self-aligned” in the sense that the location and even the configuration of the final opening is not directly defined by traditional patterning and etching techniques. Rather, a “self-aligned” contact is essentially formed in the opening that is defined by selectively etching one material, e.g., silicon dioxide, relative to other materials, such as silicon nitride sidewall spacers on adjacent gate structures. One typical self-aligned contact (SAC) process involves performing a first plasma etching process on a layer of insulating material, e.g., silicon dioxide, to define the contact opening. This first etching process is performed until the underlying etch stop layer, e.g., silicon nitride, is exposed. Thereafter, a second plasma etching process is performed on the exposed etch stop layer until such time as the underlying source/drain region that is formed in the substrate is exposed. The silicon nitride etch stop layer (which was also deposited on the upper portion of the gate structures and the sidewall spacers) needs to be highly resistant to the etch chemistry employed in the first plasma etching process performed on the insulating material, e.g., silicon dioxide, to insure the integrity of the gate encapsulation is not jeopardized. The silicon nitride etch stop layer should also be of sufficient thickness along the side of the gate structures to withstand the second plasma etch process that etches through the silicon nitride etch stop layer and exposes the source/drain region.
The first plasma etching process, which is typically performed to etch a layer of silicon dioxide, is performed using a plasma based etch process with an etch chemistry that is a combination of carbon and fluorine containing gases (e.g., C4F8/CH2F2/Ar, or C4F6/Co/Ar, etc.). Polymer formation during the first plasma etching process is a key factor in maintaining an anisotropic and vertical profile for the contact opening and in protecting the upper portion of the silicon nitride etch stop layer on the gate structures as well as the etch stop layer positioned on the sidewall spacer of the gate structure. If there is no polymer production during the first plasma etching process (the etching of the silicon dioxide insulating layer) and the second plasma etching process (the etching of the silicon nitride etch stop layer), then the upper shoulder of the silicon nitride etch stop layer may be completely consumed, which can lead to the formation of a short circuit between the gate electrode and the contact. If there is too much polymer formation during the first plasma etching process, then it may be difficult to break through the etch stop layer during the second plasma etching process that is performed to expose the source/drain region. Such a condition may result in an “open” contact which can lead to device failure.
The use of self-aligned contacts (SAC) in memory devices has been employed for several years. In a memory array, to the extent that there are defects in the formation of such self-aligned contacts (SAC) in the memory array, e.g., a short circuit was created between the conductive contact and the cells, such a problem could be readily addressed in such a memory array by using well-known redundancy schemes, i.e., redundant memory cells and repair control circuits. However, when logic circuits, such as microprocessor circuits, are involved, it is much more difficult to locate where such an error or defective contact is located, and there is limited and costly capability for fixing such problems in a logic circuit and then only when such defective contacts happen to be located in a redundant circuit block. As a result, in some cases, even one defect in forming conductive contacts to the source/drain regions of a transistor device can result in complete circuit failure with the attendant loss of yield and increased production costs. Even when repairs are possible, there is a very low success rate on such repairs. Thus, for logic circuits, the formation of self-aligned contacts (SAC) must be much more accurate and defect-free than the self-aligned contact (SAC) formation processes used in memory devices.
There have been attempts to improve the accuracy and reliability of the processes used to form self-aligned contacts (SAC). For example, current improvement methods focus on enhancing the etch selectivity between a silicon dioxide insulating layer and a silicon nitride etch stop layer by fine-tuning the plasma etch chemistry for such materials, e.g., using C4F6 or C5F8 gases with better control of the ratio of carbon to fluorine for controlling polymer generation. Another technique that has been employed to improve self-aligned contact (SAC) formation processes involves using different materials for the etch stop layer, such as silicon or carbon doped materials, silicon-rich silicon oxynitride, aluminum dioxide, etc. One other technique involves carbon doping of the silicon nitride etch stop layer to reduce the nominal etch rate of the original silicon nitride material, but this process is not effective at solving the problems mentioned above as there is still a chance of consuming the etch stop layer in problematic areas identified above. Another technique that has been employed is to try to locally increase the thickness of the etch stop layer near the upper corner of the gate structure. However, this latter approach greatly increases processing complexities and costs by requiring the performance of additional steps such as thin-film deposition, lithography, etching, etc.
The present disclosure is directed to various methods of forming self-aligned contacts (SAC) for semiconductor devices such as transistors that may avoid, or at least reduce, the effects of one or more of the problems identified above.